Rishov Sarkar

activity

20222025

most citedM

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ViT: Mixture-of-Experts Vision Transformer for Efficient Multi-task Learning with Model-Accelerator Co-design

33 citations · 56 across the 10 of their papers we have counts for

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2 papers · 1 filter

cs.AR2025

FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs

Stefan Abi-Karam, Rishov Sarkar, Suhail Basalama +2

Dataflow hardware designs enable efficient FPGA implementations via high-level synthesis (HLS), but correctly sizing first-in-first-out (FIFO) channel buffers remains challenging.…

cs.AR2025

OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs

Rishov Sarkar, Cong Hao

High-Level Synthesis (HLS) is increasingly popular for hardware design using C/C++ instead of Register-Transfer Level (RTL). To express concurrent hardware behavior in a sequential…