37 citations · 47 across the 7 of their papers we have counts for
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cs.SE2025
BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis
Surya Jasper, Minh Luu, Evan Pan +4
Hardware complexity continues to strain verification resources, motivating the adoption of machine learning (ML) methods to improve debug efficiency. However, ML-assisted debugging…
cs.LG2025
VCDiag: Classifying Erroneous Waveforms for Failure Triage Acceleration
Minh Luu, Surya Jasper, Khoi Le +4
Failure triage in design functional verification is critical but time-intensive, relying on manual specification reviews, log inspections, and waveform analyses. While machine lear…
cs.AR2025
Spec2Assertion: Automatic Pre-RTL Assertion Generation using Large Language Models with Progressive Regularization
Fenghua Wu, Evan Pan, Rahul Kande +5
SystemVerilog Assertions (SVAs) play a critical role in detecting and debugging functional bugs in digital chip design. However, generating SVAs has traditionally been a manual, la…