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cs.AR2024
An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators
Corentin Ferry, Nicolas Derumigny, Steven Derrien +1
Memory bandwidth is known to be a performance bottleneck for FPGA accelerators, especially when they deal with large multi-dimensional data-sets. A large body of work focuses on re…
cs.AR2022
Increasing FPGA Accelerators Memory Bandwidth with a Burst-Friendly Memory Layout
Corentin Ferry, Tomofumi Yuki, Steven Derrien +1
Offloading compute-intensive kernels to hardware accelerators relies on the large degree of parallelism offered by these platforms. However, the effective bandwidth of the memory i…