5 papers
ANTMAN: An Efficient and Interpretable RTL-Level Run-Time Detection Framework for Stealthy Branch Predictor Attacks on BOOM
Muhammad Hassan, Maria Mushtaq, Jaan Raik +1
Runtime detection of microarchitectural side channel attacks remains significantly underexplored in RISCV compared with x86 and ARM ISAs, posing a serious threat to critical applic…
CoG-Guided Weight Correction for Fault-Tolerant Deep Neural Networks
Bahram Parchekani, Samira Nazari, Ali Azarpeyvand +3
Deep Neural Networks (DNNs) used in safety-critical applications are vulnerable to hardware and memory faults that corrupt network weights and degrade reliability. In this paper, w…
RESQ: A Unified Framework for REliability- and Security Enhancement of Quantized Deep Neural Networks
Ali Soltan Mohammadi, Samira Nazari, Ali Azarpeyvand +5
This work proposes a unified three-stage framework that produces a quantized DNN with balanced fault and attack robustness. The first stage improves attack resilience via fine-tuni…
DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
Muhammad Hassan, Maria Mushtaq, Jaan Raik +1
RISC-V processors are becoming ubiquitous in critical applications, but their susceptibility to microarchitectural side-channel attacks is a serious concern. Detection of microarch…
SCARF: Securing Chips with a Robust Framework against Fabrication-time Hardware Trojans
Mohammad Eslami, Tara Ghasempouri, Samuel Pagliarini
The globalization of the semiconductor industry has introduced security challenges to Integrated Circuits (ICs), particularly those related to the threat of Hardware Trojans (HTs)…