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Enhancement in Reliability for Multi-core system consisting of One Instruction Cores
Shashikiran Venkatesha, Ranjani Parthasarathi
Rapid CMOS device size reduction resulted in billions of transistors on a chip have led to integration of many cores leading to many challenges such as increased power dissipation,…
A Survey of fault models and fault tolerance methods for 2D bus-based multi-core systems and TSV based 3D NOC many-core systems
Shashikiran Venkatesha, Ranjani Parthasarathi
Reliability has taken centre stage in the development of high-performance computing processors. A Surge of interest is noticeable in recent times in formulating fault and failure m…
A Survey of fault mitigation techniques for multi-core architectures
Shashikiran Venkatesha, Ranjani Parthasarathi
Fault tolerance in multi-core architecture has attracted attention of research community for the past 20 years. Rapid improvements in the CMOS technology resulted in exponential gr…