6 citations · 18 across the 13 of their papers we have counts for
13 papers
EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models
Guanglei Zhou, Chen-Chia Chang, Yikang Shen +5
Automating analog circuit topology design is essential to reduce the extensive manual effort required to meet increasingly diverse and customized application demands. Recent advanc…
CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMs
Jingyu Pan, Isaac Jacobson, Zheng Zhao +5
Modern very large-scale integration (VLSI) design requires the implementation of integrated circuits using electronic design automation (EDA) tools. Due to the complexity of EDA al…
LaMAGIC2: Advanced Circuit Formulations for Language Model-Based Analog Topology Generation
Chen-Chia Chang, Wan-Hsuan Lin, Yikang Shen +2
Automation of analog topology design is crucial due to customized requirements of modern applications with heavily manual engineering efforts. The state-of-the-art work applies a s…
A Survey of Research in Large Language Models for Electronic Design Automation
Jingyu Pan, Guanglei Zhou, Chen-Chia Chang +3
Within the rapidly evolving domain of Electronic Design Automation (EDA), Large Language Models (LLMs) have emerged as transformative technologies, offering unprecedented capabilit…
DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent
Chen-Chia Chang, Chia-Tung Ho, Yaguang Li +2
In the advanced technology nodes, the integrated design rule checker (DRC) is often utilized in place and route tools for fast optimization loops for power-performance-area. Implem…
Improving Routability Prediction via NAS Using a Smooth One-shot Augmented Predictor
Arjun Sridhar, Chen-Chia Chang, Junyao Zhang +1
Routability optimization in modern EDA tools has benefited greatly from using machine learning (ML) models. Constructing and optimizing the performance of ML models continues to be…
PatternPaint: Practical Layout Pattern Generation Using Diffusion-Based Inpainting
Guanglei Zhou, Bhargav Korrapati, Gaurav Rajavendra Reddy +5
Generating diverse VLSI layout patterns is essential for various downstream tasks in design for manufacturing, as design rules continually evolve during the development of new tech…
LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits
Chen-Chia Chang, Yikang Shen, Shaoze Fan +5
In the realm of electronic and electrical engineering, automation of analog circuit is increasingly vital given the complexity and customized requirements of modern applications. H…
PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
Qijun Zhang, Shiyu Li, Guanglei Zhou +4
Power efficiency is a critical design objective in modern microprocessor design. To evaluate the impact of architectural-level design decisions, an accurate yet efficient architect…
EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research
Jingyu Pan, Chen-Chia Chang, Zhiyao Xie +2
The application of Machine Learning (ML) in Electronic Design Automation (EDA) for Very Large-Scale Integration (VLSI) design has garnered significant research attention. Despite t…
The Dark Side: Security Concerns in Machine Learning for EDA
Zhiyao Xie, Jingyu Pan, Chen-Chia Chang +1
The growing IC complexity has led to a compelling need for design efficiency improvement through new electronic design automation (EDA) methodologies. In recent years, many unprece…
Towards Collaborative Intelligence: Routability Estimation based on Decentralized Private Data
Jingyu Pan, Chen-Chia Chang, Zhiyao Xie +5
Applying machine learning (ML) in design flow is a popular trend in EDA with various applications from design quality predictions to optimizations. Despite its promise, which has b…
Automatic Routability Predictor Development Using Neural Architecture Search
Chen-Chia Chang, Jingyu Pan, Tunhou Zhang +8
The rise of machine learning technology inspires a boom of its applications in electronic design automation (EDA) and helps improve the degree of automation in chip designs. Howeve…