4 citations · 4 across the 3 of their papers we have counts for
3 papers
Reuse Detector: Improving the Management of STT-RAM SLLCs
Roberto RodrÍguez-RodrÍguez, Javier DÍaz, Fernando Castro +8
Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-…
Forecasting lifetime and performance of a novel NVM last-level cache with compression
Carlos Escuin, Pablo Ibañez, Teresa Monreal +2
Non-volatile memory (NVM) technologies are interesting alternatives for building the on-chip Last-Level Cache (LLC). Their advantages, compared to SRAM memory, are higher density a…
L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime
Carlos Escuin, Pablo Ibañez, Teresa Monreal +2
Several emerging non-volatile (NV) memory technologies are rising as interesting alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM memory, are hi…