14 citations · 21 across the 3 of their papers we have counts for
3 papers
cs.AR2023★ 1 cited
Multiplier Optimization via E-Graph Rewriting
Andy Wanna, Samuel Coward, Theo Drane +2
Multiplier circuits account for significant resource usage in datapath-dominated circuit designs, and RTL designers continue to build bespoke hand-crafted multiplication arrays for…
cs.AR2023★ 14 cited
Low-Latency Online Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays
Muhammad Usman, Milos Ercegovac, Jeong-A Lee
Multiplication is indispensable and is one of the core operations in many modern applications including signal processing and neural networks. Conventional right-to-left (RL) multi…
cs.AR2022★ 6 cited
Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays
Muhammad Usman, Jeong-A Lee, Milos D. Ercegovac
We present a pipelined multiplier with reduced activities and minimized interconnect based on online digit-serial arithmetic. The working precision has been truncated such that $p<…