6 citations · 10 across the 6 of their papers we have counts for
6 papers
MINT: Dynamic-Precision CNN Inference with MSDF Digit-Serial Arithmetic on FPGA
Muhammad Usman, Malik Zohaib Nisar, Florian Aschauer +1
We present MINT, a dynamic-precision CNN inference accelerator based on left-to-right (LR) arithmetic. LR arithmetic computes in most-significant-digit-first manner and exposes use…
DSLR-CNN: Efficient CNN Acceleration using Digit-Serial Left-to-Right Arithmetic
Malik Zohaib Nisar, Muhammad Sohail Ibrahim, Saeid Gorgin +2
Digit-serial arithmetic has emerged as a viable approach for designing hardware accelerators, reducing interconnections, area utilization, and power consumption. However, conventio…
USEFUSE: Uniform Stride for Enhanced Performance in Fused Layer Architecture of Deep Neural Networks
Muhammad Sohail Ibrahim, Muhammad Usman, Jeong-A Lee
Convolutional Neural Networks (CNNs) are crucial in various applications, but their deployment on resource-constrained edge devices poses challenges. This study presents the Sum-of…
L2R-CIPU: Efficient CNN Computation with Left-to-Right Composite Inner Product Units
Malik Zohaib Nisar, Mohammad Sohail Ibrahim, Muhammad Usman +1
This paper proposes a composite inner-product computation unit based on left-to-right (LR) arithmetic for the acceleration of convolution neural networks (CNN) on hardware. The eff…
DSLOT-NN: Digit-Serial Left-to-Right Neural Network Accelerator
Muhammad Sohail Ibrahim, Muhammad Usman, Malik Zohaib Nisar +1
We propose a Digit-Serial Left-tO-righT (DSLOT) arithmetic based processing technique called DSLOT-NN with aim to accelerate inference of the convolution operation in the deep neur…
Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays
Muhammad Usman, Jeong-A Lee, Milos D. Ercegovac
We present a pipelined multiplier with reduced activities and minimized interconnect based on online digit-serial arithmetic. The working precision has been truncated such that $p<…