34 citations · 87 across the 11 of their papers we have counts for
11 papers
Safe-NEureka: a Hybrid Modular Redundant DNN Accelerator for On-board Satellite AI Processing
Riccardo Tedeschi, Luigi Ghionda, Alessandro Nadalini +5
Low Earth Orbit (LEO) constellations are revolutionizing the space sector, with on-board Artificial Intelligence (AI) becoming pivotal for next-generation satellites. AI accelerati…
RedMulE-FT: A Reconfigurable Fault-Tolerant Matrix Multiplication Engine
Philip Wiese, Maurus Item, Luca Bertaccini +3
As safety-critical applications increasingly rely on data-parallel floating-point computations, there is an increasing need for flexible and configurable fault tolerance in paralle…
Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing
Mattia Sinigaglia, Amirhossein Kiamarzi, Marco Bertuletti +11
Most Wearable Ultrasound (WUS) devices lack the computational power to process signals at the edge, instead relying on remote offload, which introduces latency, high power consumpt…
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti +20
Next-generation mixed-criticality Systems-on-chip (SoCs) for robotics, automotive, and space must execute mixed-criticality AI-enhanced sensor processing and control workloads, ens…
A Flexible Template for Edge Generative AI with High-Accuracy Accelerated Softmax & GELU
Andrea Belano, Yvan Tortorella, Angelo Garofalo +3
Transformer-based generative Artificial Intelligence (GenAI) models achieve remarkable results in a wide range of fields, including natural language processing, computer vision, an…
A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation
Luca Valente, Alessandro Nadalini, Asif Veeran +12
The rapid advancement of energy-efficient parallel ultra-low-power (ULP) ucontrollers units (MCUs) is enabling the development of autonomous nano-sized unmanned aerial vehicles (na…
DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training
Angelo Garofalo, Yvan Tortorella, Matteo Perotti +5
On-chip DNN inference and training at the Extreme-Edge (TinyML) impose strict latency, throughput, accuracy and flexibility requirements. Heterogeneous clusters are promising solut…
Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space
Michael Rogenmoser, Yvan Tortorella, Davide Rossi +2
Space Cyber-Physical Systems (S-CPS) such as spacecraft and satellites strongly rely on the reliability of onboard computers to guarantee the success of their missions. Relying sol…
RedMule: A Mixed-Precision Matrix-Matrix Operation Engine for Flexible and Energy-Efficient On-Chip Linear Algebra and TinyML Training Acceleration
Yvan Tortorella, Luca Bertaccini, Luca Benini +2
The increasing interest in TinyML, i.e., near-sensor machine learning on power budgets of a few tens of mW, is currently pushing toward enabling TinyML-class training as opposed to…
HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
Luca Valente, Yvan Tortorella, Mattia Sinigaglia +4
IoT applications span a wide range in performance and memory footprint, under tight cost and power constraints. High-end applications rely on power-hungry Systems-on-Chip (SoCs) fe…
RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs
Yvan Tortorella, Luca Bertaccini, Davide Rossi +2
The fast proliferation of extreme-edge applications using Deep Learning (DL) based algorithms required dedicated hardware to satisfy extreme-edge applications' latency, throughput,…