4 citations · 7 across the 2 of their papers we have counts for
2 papers
cs.CR2022★ 3 cited
Gate-Level Side-Channel Leakage Assessment with Architecture Correlation Analysis
Pantea Kiaei, Yuan Yao, Zhenyuan Liu +7
While side-channel leakage is traditionally evaluated from a fabricated chip, it is more time-efficient and cost-effective to do so during the design phase of the chip. We present…
cs.AR2022★ 4 cited
Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment
Pantea Kiaei, Zhenyuan Liu, Patrick Schaumont
Pre-silicon side-channel leakage assessment is a useful tool to identify hardware vulnerabilities at design time, but it requires many high-resolution power traces and increases th…