17 papers
Physically-Aware Preemptive Virtual Channels for Deadlock-Free AXI Networks-on-Chip
Lorenzo Leone, Luca Colagrande, Luca Benini
As many-core Systems-on-Chip (SoCs) continue to scale, Networks-on-Chip (NoCs) must sustain increasingly high memory bandwidth while preserving deadlock freedom. In AXI4 systems, p…
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
Lorenzo Leone, Philip Wiese, Gamze Ä°slamoÄlu +4
We present Chimera, a flexible and scalable Microcontroller Unit (MCU) designed to accelerate real-time inference of rapidly evolving transformer-based models at the ultra-low-powe…
O-POPE: High-Frequency Pipelined Outer Product based GEMM acceleration with minimal buffering overhead
Danilo Cammarata, Angelo Garofalo, Luca Benini
General matrix multiply (GEMM) dominates both execution time and energy consumption of modern machine learning (ML) workloads, placing increasing pressure on hardware efficiency. W…
EPAC: The Last Dance
Filippo Mantovani, Fabio Banchelli, Pablo Vizcaino +36
This paper presents EPAC, a RISC-V-based accelerator chip developed within the European Processor Initiative (EPI) as part of a multi-year, multi-partner effort to build a European…
HyperCroc: End-to-End Open-Source RISC-V MCU with a Plug-In Interface for Domain-Specific Accelerators
Philippe Sauter, Thomas Benz, Paul Scheffler +1
Domain-Specific architectures with accelerators for machine learning and signal processing require efficient bulk data movement and high-bandwidth access to large datasets. Such ca…
Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs
Axel Vanoni, Philippe Sauter, Paul Scheffler +4
Recent announcements have shown the viability of end-to-end open-source (OS) Linux-capable RISC-V systems on chip (SoCs). However, practical application and software development pl…