5 papers
Physically-Aware Preemptive Virtual Channels for Deadlock-Free AXI Networks-on-Chip
Lorenzo Leone, Luca Colagrande, Luca Benini
As many-core Systems-on-Chip (SoCs) continue to scale, Networks-on-Chip (NoCs) must sustain increasingly high memory bandwidth while preserving deadlock freedom. In AXI4 systems, p…
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
Lorenzo Leone, Philip Wiese, Gamze Ä°slamoÄlu +4
We present Chimera, a flexible and scalable Microcontroller Unit (MCU) designed to accelerate real-time inference of rapidly evolving transformer-based models at the ultra-low-powe…
A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators
Luca Colagrande, Lorenzo Leone, Chen Wu +3
The exponential increase in Machine Learning (ML) model size and complexity has driven unprecedented demand for high-performance acceleration systems. As technology scaling enables…
Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond
Paul Scheffler, Thomas Benz, Tim Fischer +3
We present a roadmap for open-source chiplet-based RISC-V systems targeting high-performance computing and artificial intelligence, aiming to close the performance gap to proprieta…
Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration
Luca Colagrande, Lorenzo Leone, Maximilian Coco +2
The growing computational demands of machine learning (ML) workloads have driven the design of ML accelerators aiming at an optimal tradeoff between efficiency and flexibility. A w…