3 citations · 3 across the 2 of their papers we have counts for
2 papers
cs.AR2023★ 3 cited
VPU-EM: An Event-based Modeling Framework to Evaluate NPU Performance and Power Efficiency at Scale
Charles Qi, Yi Wang, Hui Wang +18
State-of-art NPUs are typically architected as a self-contained sub-system with multiple heterogeneous hardware computing modules, and a dataflow-driven programming model. There la…
cs.LG2022
Towards Optimal VPU Compiler Cost Modeling by using Neural Networks to Infer Hardware Performances
Ian Frederick Vigogne Goodbody Hunter, Alessandro Palla, Sebastian Eusebiu Nagy +2
Calculating the most efficient schedule of work in a neural network compiler is a difficult task. There are many parameters to be accounted for that can positively or adversely aff…