13 citations · 24 across the 13 of their papers we have counts for
13 papers
Vision-centric generative AI models: A software-hardware perspective
Eleni Tselepi, Cristian Sestito, Shady Agwa +1
Vision generative artificial intelligence (AI) has emerged as one of the most rapidly advancing areas of deep learning. The explosion of multimodal models has made them widely asso…
BenDi: An Energy-Efficient Quasi-Stochastic Systolic Architecture for Edge Bioelectronics
Bochen Ye, Yihan Pan, Shady Agwa +1
Continuous long-term monitoring and diagnosis of biomedical signals, such as electrocardiograms (ECGs), can help mitigate an increasing threat to public health. Artificial Intellig…
DISCA: A Digital In-memory Stochastic Computing Architecture Using A Compressed Bent-Pyramid Format
Shady Agwa, Yikang Shen, Shiwei Wang +1
Nowadays, we are witnessing an Artificial Intelligence revolution that dominates the technology landscape in various application domains, such as healthcare, robotics, automotive,…
OISMA: On-the-fly In-memory Stochastic Multiplication Architecture for Matrix-Multiplication Workloads
Shady Agwa, Yihan Pan, Georgios Papandroulidakis +1
Artificial intelligence (AI) models are currently driven by a significant upscaling of their complexity, with massive matrix-multiplication workloads representing the major computa…
3D-TrIM: A Memory-Efficient Spatial Computing Architecture for Convolution Workloads
Cristian Sestito, Ahmed J. Abdelmaksoud, Shady Agwa +1
The Von Neumann bottleneck, which relates to the energy cost of moving data from memory to on-chip core and vice versa, is a serious challenge in state-of-the-art AI architectures,…
A Hybrid Edge Classifier: Combining TinyML-Optimised CNN with RRAM-CMOS ACAM for Energy-Efficient Inference
Kieran Woodward, Eiman Kanjo, Georgios Papandroulidakis +2
In recent years, the development of smart edge computing systems to process information locally is on the rise. Many near-sensor machine learning (ML) approaches have been implemen…
L-Sort: On-chip Spike Sorting with Efficient Median-of-Median Detection and Localization-based Clustering
Yuntao Han, Yihan Pan, Xiongfei Jiang +4
Spike sorting is a critical process for decoding large-scale neural activity from extracellular recordings. The advancement of neural probes facilitates the recording of a high num…
DiP: A Scalable, Energy-Efficient Systolic Array for Matrix Multiplication Acceleration
Ahmed J. Abdelmaksoud, Shady Agwa, Themis Prodromakis
Transformers are gaining increasing attention across Natural Language Processing (NLP) application domains due to their outstanding accuracy. However, these data-intensive models a…
A 9T4R RRAM-Based ACAM for Analogue Template Matching at the Edge
Georgios Papandroulidakis, Shady Agwa, Ahmet Cirakoglu +1
The continuous shift of computational bottlenecks to the memory access and data transfer, especially for AI applications, poses the urgent needs of re-engineering the computer arch…
TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Architecture and Hardware Implementation
Cristian Sestito, Shady Agwa, Themis Prodromakis
Modern hardware architectures for Convolutional Neural Networks (CNNs), other than targeting high performance, aim at dissipating limited energy. Reducing the data movement cost be…
TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Dataflow and Analytical Modelling
Cristian Sestito, Shady Agwa, Themis Prodromakis
In order to follow the ever-growing computational complexity and data intensity of state-of-the-art AI models, new computing paradigms are being proposed. These paradigms aim at ac…
An Energy-efficient Capacitive-RRAM Content Addressable Memory
Yihan Pan, Adrian Wheeldon, Mohammed Mughal +3
Content addressable memory is popular in intelligent computing systems as it allows parallel content-searching in memory. Emerging CAMs show a promising increase in bitcell density…
A CMOS-based Characterisation Platform for Emerging RRAM Technologies
Andrea Mifsud, Jiawei Shen, Peilong Feng +11
Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit des…