14 papers
VeriChat: An Agentic Conversational AI Assistant for Hardware Security Verification
Dipayan Saha, Khan Thamid Hasan, Shams Tarek +3
Hardware security verification is a multi-stage process in which engineers must navigate complex design analyses, threat considerations, and verification strategies. They often nee…
ChartZero: Synthetic Priors Enable Zero Shot Chart Data Extraction
Md Touhidul Islam, Yasir Mahmud, Sujan Kumar Saha +2
Automated data extraction from line charts remains fundamentally bottlenecked by extreme stylistic diversity and a severe scarcity of comprehensively annotated, real-world datasets…
CircuitFormer: A Circuit Language Model for Analog Topology Design from Natural Language Prompt
Md Touhidul Islam, Sujan Kumar Saha, Farimah Farahmandi +1
Automating analog circuit design remains a longstanding challenge in Electronic Design Automation (EDA). While Transformer-based Large Language Models (LLMs) have revolutionized so…
Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
Tanvir Rahman, Shuvagata Saha, Ahmed Y. Alhurubi +3
Increasing system-on-chip (SoC) heterogeneity, deep hardware/software integration, and the proliferation of third-party intellectual property (IP) have brought security validation…
LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification
Md Ajoad Hasan, Dipayan Saha, Khan Thamid Hasan +5
The growing complexity of modern system-on-chip (SoC) and IP designs is making security assurance difficult day by day. One of the fundamental steps in the pre-silicon security ver…
Assertain: Automated Security Assertion Generation Using Large Language Models
Shams Tarek, Dipayan Saha, Khan Thamid Hasan +3
The increasing complexity of modern system-on-chip designs amplifies hardware security risks and makes manual security property specification a major bottleneck in formal property…