7 papers · 1 filter
VeriChat: An Agentic Conversational AI Assistant for Hardware Security Verification
Dipayan Saha, Khan Thamid Hasan, Shams Tarek +3
Hardware security verification is a multi-stage process in which engineers must navigate complex design analyses, threat considerations, and verification strategies. They often nee…
Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
Tanvir Rahman, Shuvagata Saha, Ahmed Y. Alhurubi +3
Increasing system-on-chip (SoC) heterogeneity, deep hardware/software integration, and the proliferation of third-party intellectual property (IP) have brought security validation…
LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification
Md Ajoad Hasan, Dipayan Saha, Khan Thamid Hasan +5
The growing complexity of modern system-on-chip (SoC) and IP designs is making security assurance difficult day by day. One of the fundamental steps in the pre-silicon security ver…
Assertain: Automated Security Assertion Generation Using Large Language Models
Shams Tarek, Dipayan Saha, Khan Thamid Hasan +3
The increasing complexity of modern system-on-chip designs amplifies hardware security risks and makes manual security property specification a major bottleneck in formal property…
SVAgent: AI Agent for Hardware Security Verification Assertion
Rui Guo, Avinash Ayalasomayajula, Henian Li +3
Verification using SystemVerilog assertions (SVA) is one of the most popular methods for detecting circuit design vulnerabilities. However, with the globalization of integrated cir…
SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
Dipayan Saha, Shams Tarek, Hasan Al Shaikh +8
Ensuring the security of complex system-on-chips (SoCs) designs is a critical imperative, yet traditional verification techniques struggle to keep pace due to significant challenge…