5 papers
VeriChat: An Agentic Conversational AI Assistant for Hardware Security Verification
Dipayan Saha, Khan Thamid Hasan, Shams Tarek +3
Hardware security verification is a multi-stage process in which engineers must navigate complex design analyses, threat considerations, and verification strategies. They often nee…
Assertain: Automated Security Assertion Generation Using Large Language Models
Shams Tarek, Dipayan Saha, Khan Thamid Hasan +3
The increasing complexity of modern system-on-chip designs amplifies hardware security risks and makes manual security property specification a major bottleneck in formal property…
SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
Dipayan Saha, Shams Tarek, Hasan Al Shaikh +8
Ensuring the security of complex system-on-chips (SoCs) designs is a critical imperative, yet traditional verification techniques struggle to keep pace due to significant challenge…
BugWhisperer: Fine-Tuning LLMs for SoC Hardware Vulnerability Detection
Shams Tarek, Dipayan Saha, Sujan Kumar Saha +1
The current landscape of system-on-chips (SoCs) security verification faces challenges due to manual, labor-intensive, and inflexible methodologies. These issues limit the scalabil…
ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification
Dipayan Saha, Hasan Al Shaikh, Shams Tarek +1
Current hardware security verification processes predominantly rely on manual threat modeling and test plan generation, which are labor-intensive, error-prone, and struggle to scal…