12 papers
A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
Wenji Fang, Jing Wang, Yao Lu +4
Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications. Most recently, foundation AI…
ComPart: Community-Guided Post-Coarsening for High-Quality Hypergraph Partitioning
Yugao Zhu, Zhicheng Guo, Yuchao Wu +3
Hypergraph partitioning is a critical step in the design of complex embedded systems, essential for optimizing task mapping on heterogeneous MPSoCs and enabling multi-FPGA prototyp…
IMPart: Integration of Memetic Operations into Multi-Level Framework for Large-k-Way Hypergraph Partitioning
Yugao Zhu, Zhicheng Guo, Shang Liu +3
The problem of k-way hypergraph partitioning is fundamental with significant applications in various fields, including VLSI design and scientific computing. State-of-the-art hyperg…
RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models
Jing Wang, Shang Liu, Wenji Fang +3
LLM-based RTL generation and reasoning is a promising direction for hardware design automation. High-quality benchmarks are critical infrastructure for tracking progress in this di…
AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications
Yuchao Wu, Wenji Fang, Jing Wang +3
Assertion-based verification (ABV) is a cornerstone of modern hardware design, yet manually translating design intent into formal SystemVerilog Assertions (SVAs) remains labor-inte…
RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision
Jing Wang, Shang Liu, Hangan Zhou +1
This paper introduces RTL-BenchMT, an agentic framework for dynamically maintaining RTL generation benchmarks. Large Language Models (LLMs) assisted automated RTL generation is one…