2 papers
cs.AR2022
Freeway to Memory Level Parallelism in Slice-Out-of-Order Cores
Rakesh Kumar, Mehdi Alipour, David Black-Schaffer
Exploiting memory level parallelism (MLP) is crucial to hide long memory and last level cache access latencies. While out-of-order (OoO) cores, and techniques building on them, are…
cs.AR2020
Page Tables: Keeping them Flat and Hot (Cached)
Chang Hyun Park, Ilias Vougioukas, Andreas Sandberg +1
As memory capacity has outstripped TLB coverage, large data applications suffer from frequent page table walks. We investigate two complementary techniques for addressing this cost…