5 citations · 6 across the 5 of their papers we have counts for
5 papers
Efficiently Synthesizing Lowest Cost Rewrite Rules for Instruction Selection
Ross Daly, Caleb Donovick, Caleb Terrill +4
Compiling programs to an instruction set architecture (ISA) requires a set of rewrite rules that map patterns consisting of compiler instructions to patterns consisting of ISA inst…
PEak: A Single Source of Truth for Hardware Design and Verification
Caleb Donovick, Ross Daly, Jackson Melchert +4
Domain-specific languages for hardware can significantly enhance designer productivity, but sometimes at the cost of ease of verification. On the other hand, ISA specification lang…
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays
Jackson Melchert, Keyi Zhang, Yuchen Mei +3
The architecture of a coarse-grained reconfigurable array (CGRA) interconnect has a significant effect on not only the flexibility of the resulting accelerator, but also its power,…
Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays
Jackson Melchert, Yuchen Mei, Kalhan Koul +3
While coarse-grained reconfigurable arrays (CGRAs) have emerged as promising programmable accelerator architectures, pipelining applications running on CGRAs is required to ensure…
Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis
Jackson Melchert, Kathleen Feng, Caleb Donovick +5
The architecture of a coarse-grained reconfigurable array (CGRA) processing element (PE) has a significant effect on the performance and energy efficiency of an application running…