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20212024
most citedExperimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array

1 citations · 2 across the 7 of their papers we have counts for

collaborators

7 papers

cs.ET2024

In-Memory Mirroring: Cloning Without Reading

Simranjeet Singh, Ankit Bende, Chandan Kumar Jha +4

In-memory computing (IMC) has gained significant attention recently as it attempts to reduce the impact of memory bottlenecks. Numerous schemes for digital IMC are presented in the…

cs.ET2023★ 1 cited

Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array

Ankit Bende, Simranjeet Singh, Chandan Kumar Jha +10

Memristor-aided logic (MAGIC) design style holds a high promise for realizing digital logic-in-memory functionality. The ability to implement a specific gate in a MAGIC design styl…

cs.ET2023★ 1 cited

MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory

Simranjeet Singh, Chandan Kumar Jha, Ankit Bende +4

Existing logic-in-memory (LiM) research is limited to generating mappings and micro-operations. In this paper, we present~\emph{MemSPICE}, a novel framework that addresses this gap…

cs.ET2023

Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style

Simranjeet Singh, Chandan Kumar Jha, Ankit Bende +5

Memristor-based logic-in-memory (LiM) has become popular as a means to overcome the von Neumann bottleneck in traditional data-intensive computing. Recently, the memristor-aided lo…

cs.ET2023

Finite State Automata Design using 1T1R ReRAM Crossbar

Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha +6

Data movement costs constitute a significant bottleneck in modern machine learning (ML) systems. When combined with the computational complexity of algorithms, such as neural netwo…

cs.AR2022

A Fresh Perspective on DNN Accelerators by Performing Holistic Analysis Across Paradigms

Tom Glint, Chandan Kumar Jha, Manu Awasthi +1

Traditional computers with von Neumann architecture are unable to meet the latency and scalability challenges of Deep Neural Network (DNN) workloads. Various DNN accelerators based…

cs.AR2021

Zero Aware Configurable Data Encoding by Skipping Transfer for Error Resilient Applications

Chandan Kumar Jha, Shreyas Singh, Riddhi Thakker +2

In this paper, we propose Zero Aware Configurable Data Encoding by Skipping Transfer (ZAC-DEST), a data encoding scheme to reduce the energy consumption of DRAM channels, specifica…