2 papers
cs.AR2024
Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension
George-Marios Fragkoulis, Nikos Karystinos, George Papadimitriou +1
This paper presents the implementation and evaluation of the H (hypervisor) extension for the RISC-V instruction set architecture (ISA) on top of the gem5 microarchitectural simula…
cs.AR2021
Towards Accurate Performance Modeling of RISC-V Designs
Odysseas Chatzopoulos, George-Marios Fragkoulis, George Papadimitriou +1
Microprocessor design, debug, and validation research and development are increasingly based on modeling and simulation at different abstraction layers. Microarchitecture-level sim…