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20242026
most citedLeveraging ASIC AI Chips for Homomorphic Encryption

1 citations · 1 across the 6 of their papers we have counts for

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cs.AR2026

SCALE-Sim EVA: Design Principles for an Extensible, Visualizable, and Adaptable Accelerator Simulation Framework

Jingtian Dang, Ritik Raj, Tushar Krishna

Modern AI accelerators increasingly combine heterogeneous compute units, hierarchical memories, local buffers, and specialized data movement paths. This diversity makes fixed accel…

cs.AR2026

Enabling AI ASICs for Zero Knowledge Proof

Jianming Tong, Jingtian Dang, Simon Langowski +6

Zero-knowledge proof (ZKP) provers remain costly because multi-scalar multiplication (MSM) and number-theoretic transforms (NTTs) dominate runtime as they need significant computat…

cs.AR2026

SCALE-Sim TPU: Validating and Extending SCALE-Sim for TPUs

Jingtian Dang, Ritik Raj, Changhai Man +2

Cycle-accurate simulators are widely used to study systolic accelerators, yet their accuracy and usability are often limited by weak validation against real hardware and poor integ…

cs.AR2026

MINISA: Minimal Instruction Set Architecture for Next-gen Reconfigurable Inference Accelerator

Jianming Tong, Devansh Jain, Yujie Li +2

Modern reconfigurable AI accelerators rely on rich mapping and data-layout flexibility to sustain high utilization across matrix multiplication, convolution, and emerging applicati…

cs.AR2024

FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching

Jianming Tong, Anirudh Itagi, Prasanth Chatarasi +1

The inference of ML models composed of diverse structures, types, and sizes boils down to the execution of different dataflows (i.e. different tiling, ordering, parallelism, and sh…