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cs.AR2026
SUSpMV: A High Frequency Sparse Matrix Vector Multiplier on HBM Enabled FPGA written in SUS
Lennart Van Hirtum, David Volz, Andreas Koch +1
SUSpMV is a Sparse Matrix Vector multiplication (SpMV) accelerator written in the upcoming HDL SUS. By leveraging SUS's unique latency counting and inference mechanism, SUSpMV coul…
cs.AR2023★ 1 cited
Computing and Compressing Electron Repulsion Integrals on FPGAs
Xin Wu, Tobias Kenter, Robert Schade +2
The computation of electron repulsion integrals (ERIs) over Gaussian-type orbitals (GTOs) is a challenging problem in quantum-mechanics-based atomistic simulations. In practical si…