2 papers
cs.AR2026
'1'-bit Count-based Sorting Unit to Reduce Link Power in DNN Accelerators
Ruichi Han, Yizhi Chen, Tong Lei +2
Interconnect power consumption remains a bottleneck in Deep Neural Network (DNN) accelerators. While ordering data based on '1'-bit counts can mitigate this via reduced switching a…
cs.AR2021
Synthesis of Predictable Global NoC by Abutment in Synchoros VLSI Design
Jordi Altayó González, Dimitrios Stathis, Ahmed Hemani
Synchoros VLSI design style has been proposed as an alternative to the standard cell best design style; the word synchoros is derived from the Greek word choros for space. Synchori…