most citedInnovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies

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cs.ET2021

Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor

Chi-Shuen Lee, Brian Cline, Saurabh Sinha +2

We present a DevIce-to-System Performance EvaLuation (DISPEL) workflow that integrates transistor and interconnect modeling, parasitic extraction, standard cell library characteriz…