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Xiang Chen

19 papers hereh-index 14524 citations29 works total

Matching runs newest-first, so older work may not be attached to this profile yet.

author position
  • middle author18
  • last author1

Across the 19 of 19 papers where every author was matched, so the position is known.

fields
  • cs.SE14
  • cs.AR3
  • cs.CR2
same name
  • Xiang Chen — 163 papers
  • Xiang Chen — 26 papers, h 4
  • Xiang Chen — 24 papers, h 16
  • Xiang Chen — 24 papers, h 20
  • Xiang Chen — 20 papers, h 32
  • Xiang Chen — 15 papers, h 4

Either other researchers who publish under this name, or the same person where the external sources have not merged their records.

identity via Semantic Scholar / OpenAlex

activity
20212026
most citedFine-grained Pseudo-code Generation Method via Code Feature Extraction and Transformer

5 citations · 25 across the 19 of their papers we have counts for

collaborators
Showing 2026Show all

4 papers · 1 filter

cs.AR2026

Quality over Quantity: Diversity-Aware Data Selection for Efficient Verilog Code Generation

Yiheng Shen, Wei Zheng, Xiao Wei +3

Large Language Models (LLMs) have shown remarkable potential in Verilog code generation, yet existing datasets contain con siderable noise and redundancy. Prior data selection meth…

cs.CR2026

Unsaid, Unsafe? Implicit Security Obligations in LLM-Based RTL Code Generation

Guang Yang, Xing Hu, Xiang Chen +1

Large Language Models (LLMs) generate register-transfer-level (RTL) code with rapidly improving functional correctness. Security of LLM-generated code, however, has been studied ma…

cs.SE2026

Execution-Anchored Hallucination Calibration Reranking for Verilog Code Generation

Guang Yang, Xing Hu, Xiang Chen +2

Large Language Models (LLMs) have demonstrated remarkable capabilities in code generation, yet their performance degrades significantly on low-resource Hardware Description Languag…

cs.SE2026

Semantic Consensus Decoding: Backdoor Defense for Verilog Code Generation

Guang Yang, Xing Hu, Xiang Chen +1

Large language models (LLMs) for Verilog code generation are increasingly adopted in hardware design, yet remain vulnerable to backdoor attacks where adversaries inject malicious t…

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Not affiliated with arXiv. Researcher data from Semantic Scholar (ODC-BY) and OpenAlex.