activity
20192023
most citedPARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance

35 citations · 47 across the 7 of their papers we have counts for

collaborators

7 papers

cs.HC2023

PwR: Exploring the Role of Representations in Conversational Programming

Pradyumna YM, Vinod Ganesan, Dinesh Kumar Arumugam +7

Large Language Models (LLMs) have revolutionized programming and software engineering. AI programming assistants such as GitHub Copilot X enable conversational programming, narrowi…

cs.CR2023★ 4 cited

A Survey of Security Concerns and Countermeasures in Modern Micro-architectures with Transient Execution

Nikhilesh Singh, Vinod Ganesan, Chester Rebeiro

In the last two decades, the evolving cyber-threat landscape has brought to center stage the contentious tradeoffs between the security and performance of modern microprocessors. T…

cs.CR2022★ 4 cited

Efficient ML Models for Practical Secure Inference

Vinod Ganesan, Anwesh Bhattacharya, Pratyush Kumar +3

ML-as-a-service continues to grow, and so does the need for very strong privacy guarantees. Secure inference has emerged as a potential solution, wherein cryptographic primitives a…

cs.LG2021★ 2 cited

SuperShaper: Task-Agnostic Super Pre-training of BERT Models with Variable Hidden Dimensions

Vinod Ganesan, Gowtham Ramesh, Pratyush Kumar

Task-agnostic pre-training followed by task-specific fine-tuning is a default approach to train NLU models. Such models need to be deployed on devices across the cloud and the edge…

cs.AR2021

Design and Scaffolded Training of an Efficient DNN Operator for Computer Vision on the Edge

Vinod Ganesan, Pratyush Kumar

Massively parallel systolic arrays and resource-efficient depthwise separable convolutions are two promising techniques to accelerate DNN inference on the edge. Interestingly, thei…

cs.AR2021★ 2 cited

FuSeConv: Fully Separable Convolutions for Fast Inference on Systolic Arrays

Surya Selvam, Vinod Ganesan, Pratyush Kumar

Both efficient neural networks and hardware accelerators are being explored to speed up DNN inference on edge devices. For example, MobileNet uses depthwise separable convolution t…

cs.CR2019★ 35 cited

PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance

Muhammad Arsath K F, Vinod Ganesan, Rahul Bodduna +1

The power consumption of a microprocessor is a huge channel for information leakage. While the most popular exploitation of this channel is to recover cryptographic keys from embed…