activity
20212026
most citedBlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows

124 citations · 320 across the 59 of their papers we have counts for

collaborators

67 papers

cs.CR2026

HULK: An Efficient Algorithm for Enabling Fast Bulk Bitwise Operations on Homomorphically Encrypted Data

Mayank Kabra, Phillip Widdowson, Harshita Gupta +9

A wide range of important cloud applications, e.g., database analytics, graph analytics, and genome analysis, spend a considerable amount of time performing bulk bitwise operations…

cs.AR2026

Understanding the Power Consumption of Modern High Bandwidth Memory: Experimental Analysis and Modeling Using Real HBM2 DRAM Chips

Ataberk Olgun, Spiros Galanopoulos, Andreas Kosmas Kakolyris +4

We perform the first comprehensive experimental characterization of power consumed by real HBM2 DRAM chips. Our extensive characterization yields 1) the empirical basis for develop…

cs.CR2026

MORDOR: Mitigating Overheads of Read Disturbance Preventive Operations via Elastic Refresh Scheduling

Maria Makeenkova, Ataberk Olgun, F. Nisa Bostancı +3

Modern DRAM chips are susceptible to read disturbance phenomena such as RowHammer, where repeatedly accessing (hammering) a row of DRAM cells (i.e., a DRAM row) induces bitflips in…

cs.AR2026

Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller

Harsh Songara, Konstantinos Kanellopoulos, F. Nisa Bostancı +6

DRAM continues to limit the performance, energy efficiency, and robustness of modern systems. Many prior works propose DRAM techniques that support in-DRAM computation, improve mem…

cs.AR2026

PipeDRAM: A Data-Transposition-Free Processing-Using-DRAM Architecture with Hardware/Software Pipelining

Geraldo F. Oliveira, Ataberk Olgun, Ismail Emir Yüksel +6

Processing-using-DRAM (PUD) architectures exploit the analog operational properties of DRAM to perform bulk bitwise Boolean and arithmetic operations inside memory arrays by organi…

cs.AR2026

CertiFlash: A Formal Verification Framework for Flash Translation Layers in Computational Solid State Drives

Harshita Gupta, Mayank Kabra, Rakesh Nadig +10

Data-intensive applications move large amounts of data from storage to the compute unit, incurring significant data movement overhead. Storage-centric computing reduces this overhe…

cs.AR2026

Demystifying DRAM Read Disturbance: Bridging the Gap Between Experimental Characterization and Device-Level Modeling of RowHammer and RowPress Phenomena

Haocong Luo, Longda Zhou, Ataberk Olgun +5

DRAM read disturbance, like RowHammer and RowPress, is a critical robustness issue where accessing DRAM can cause unintended bitflips in other unaccessed DRAM locations. DRAM read…

cs.CR2026

ColumnKeeper: Efficient Solutions to the ColumnDisturb Vulnerability in DRAM-based Systems

Andreas Kosmas Kakolyris, F. Nisa Bostanci, Ataberk Olgun +7

Modern DRAM chips are vulnerable to read disturbance phenomena such as RowHammer and RowPress, which induce bitflips after accessing nearby rows a certain number of times (the read…

cs.AR2026

Clutch: High Performance Vector-Scalar Comparison using DRAM via Chunked Temporal Coding

Daichi Tokuda, Tatsuya Kubo, Ismail Emir Yuksel +8

Vector-scalar comparison is a fundamental computation primitive that compares each element in a vector against a single scalar value. It is widely used in various data-intensive wo…

cs.AR2026

DejaVu: Why You Should Write to Your DRAM Rows Twice, Carefully

Haocong Luo, İsmail Emir Yüksel, Ataberk Olgun +4

We provide the first experimental demonstration of DejaVu, a phenomenon where the data previously written to DRAM cells affects DRAM's vulnerability to read disturbance. Our experi…

cs.AR2026

Ramulator 2.1: A Composable Memory System Simulator for Modern DRAM Systems

Haocong Luo, F. Nisa Bostancı, Ataberk Olgun +4

Ramulator 2.1 is a major overhaul of Ramulator 2.0 that substantially improves the simulator in three directions: 1) support of modern and emerging DRAM and memory-controller featu…

cs.CR2026

Memory-Centric Computing: Security Benefits and Challenges of Processing-in-DRAM

Ismail Emir Yuksel, F. Nisa Bostanci, Ataberk Olgun +1

Today's computing systems are processor-centric: they require frequent data movement between processing elements (e.g., CPU) and main memory (DRAM), leading to significant ineffici…

cs.AR2026

PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems

Daichi Tokuda, İsmail Emir Yüksel, Tatsuya Kubo +7

Processing-using-DRAM (PuD) is a promising computation paradigm that alleviates frequent data movement between main memory and processing units by using each DRAM column as a compu…

cs.AR2026

In-DRAM Signature Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Off-The-Shelf DRAM Chips

Umut Baser, Ismail Emir Yuksel, F. Nisa Bostanci +7

We experimentally demonstrate that it is possible to generate unique, repeatable, and device-specific signatures suitable for use as Physical Unclonable Function (PUF) responses in…

cs.AR2026

A Modern Large-Scale Memory Characterization Laboratory

Ataberk Olgun, Haocong Luo, Ismail Emir Yuksel +3

Real memory chip characterization yields insights into fundamental operational characteristics of modern memory, enabling new mechanisms that improve memory performance, robustness…

cs.CR2026

ScaleDisturb: Exploiting Temporal Asymmetry to Amplify Read Disturbance in Modern DRAM Chips

Jikun Wang, Haocong Luo, Ataberk Olgun +6

DRAM suffers from read disturbance phenomena (e.g., RowHammer and RowPress), where repeatedly accessing or continuously keeping open a DRAM row (aggressor row) induces bitflips in…

cs.AR2026

DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips

Ataberk Olgun, F. Nisa Bostanci, Ismail Emir Yuksel +4

State-of-the-art DRAM read disturbance mitigations rely on the read disturbance threshold (RDT) (e.g., the number of aggressor row activations needed to induce the first read distu…

cs.AR2025

In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips

Ismail Emir Yuksel, Ataberk Olgun, F. Nisa Bostanci +5

In this work, we experimentally demonstrate that it is possible to generate true random numbers at high throughput and low latency in commercial off-the-shelf (COTS) DRAM chips by…

cs.AR2025

ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems

İsmail Emir Yüksel, Ataberk Olgun, F. Nisa Bostancı +3

We experimentally demonstrate a new widespread read disturbance phenomenon, ColumnDisturb, in real commodity DRAM chips. By repeatedly opening or keeping a DRAM row (aggressor row)…

cs.AR2025

Cleaning up the Mess: Re-Evaluating the Real-System Modeling Accuracy of Ramulator 2.0

F. Nisa Bostanci, Haocong Luo, Ataberk Olgun +4

A MICRO 2024 best paper runner-up publication (the Mess paper) with all three artifact badges awarded (including ``Reproducible'') proposes a new benchmark to evaluate real and sim…

cs.AR2025

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques

Oğuzhan Canpolat, Ataberk Olgun, David Novo +2

DRAM is a critical component of modern computing systems. Recent works propose numerous techniques (that we call DRAM techniques) to enhance DRAM-based computing systems' throughpu…

cs.AR2025

PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips

Ismail Emir Yuksel, Akash Sood, Ataberk Olgun +6

Processing-using-DRAM (PuD) is a promising paradigm for alleviating the data movement bottleneck using DRAM's massive internal parallelism and bandwidth to execute very wide operat…

cs.AR2025

Memory-Centric Computing: Solving Computing's Memory Problem

Onur Mutlu, Ataberk Olgun, Ismail Emir Yuksel

Computing has a huge memory problem. The memory system, consisting of multiple technologies at different levels, is responsible for most of the energy consumption, performance bott…

cs.CR2025

Understanding and Mitigating Covert Channel and Side Channel Vulnerabilities Introduced by RowHammer Defenses

F. Nisa Bostancı, Oğuzhan Canpolat, Ataberk Olgun +5

DRAM chips are vulnerable to read disturbance phenomena (e.g., RowHammer and RowPress), where repeatedly accessing or keeping open a DRAM row causes bitflips in nearby rows. Attack…