19 papers
CHORUS: Complementary Experts for High-Coverage Testbench Stimulus Generation
Hejia Zhang, Sheng Lu, Zhongming Yu +3
Large language models (LLMs) have advanced code generation, where executable feedback provides a more reliable learning signal than textual imitation alone. Hardware verification i…
SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes
Chia-Tung Ho, Haoyu Yang, Guanglei Zhou +6
As semiconductor manufacturing advances toward sub-2nm nodes, local place-and-route (P&R) design-rule violation (DRV) fixing is increasingly limited by complex rule interactions, d…
EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair
Bing-Yue Wu, Chia-Tung Ho, Haoyu Yang +2
Design rule check (DRC) closure remains a major bottleneck in advanced-node physical design. Although detailed routers are rule-aware, residual design rule violations (DRVs) often…
PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM/VLM Agents for VLSI Physical Design
Qiufeng Li, Rongqian Chen, Quan Cheng +6
The paper presents PDAGENT-BENCH, a benchmark suite and workflow framework for evaluating large language model and vision‑language model agents on VLSI physical design tasks, cover…
AUTOGATE: Automated Clock Gating via Toggling-Aware LLM-based RTL Rewriting
Yiting Wang, Chenhui Deng, Chia-Tung Ho +6
Fine-grain clock gating (FGCG) is among the most effective techniques for reducing dynamic power, yet current FGCG optimization flows remain largely manual. Recent LLM-based RTL op…
LLM4Cov: Execution-Aware Agentic Learning for High-coverage Testbench Generation
Hejia Zhang, Zhongming Yu, Chia-Tung Ho +3
Execution-aware LLM agents offer a promising paradigm for learning from tool feedback, but such feedback can be expensive and slow to obtain, making online reinforcement learning (…