Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths

Vinamra Benara, Ziaul Choudhury, Suresh Purini +1

High-level synthesis (HLS) has received significant attention in recent years, improving programmability for FPGAs. PolyMage is a domain-specific language (DSL) for image processin…