37 citations · 86 across the 16 of their papers we have counts for
17 papers
Campaign Diagrams: Visualizing the March Through the Phases of a Workload
Toluwanimi O. Odemuyiwa, John D. Owens, Michael Pellauer +1
We present campaign diagrams, a visualization technique for phase-level analysis of resource utilization and bottlenecks in modern workloads. Existing tools have a trade-off: roofl…
Mambalaya: Einsum-Based Fusion Optimizations on State-Space Models
Toluwanimi O. Odemuyiwa, John D. Owens, Joel S. Emer +1
Mamba is an emerging, complex workload with various short-range and long-range dependencies, nonlinearities, and elementwise computations that are unable to run at near-peak speeds…
HaShiFlex: A High-Throughput Hardened Shifter DNN Accelerator with Fine-Tuning Flexibility
Jonathan Herbst, Michael Pellauer, Sherief Reda
We introduce a high-throughput neural network accelerator that embeds most network layers directly in hardware, minimizing data transfer and memory usage while preserving a degree…
HARP: A Taxonomy for Heterogeneous and Hierarchical Processors for Mixed-reuse Workloads
Raveesh Garg, Michael Pellauer, Tushar Krishna
Artificial intelligence (AI) application domains consist of a mix of tensor operations with high and low arithmetic intensities (aka reuse). Hierarchical (i.e. compute along multip…
FuseMax: Leveraging Extended Einsums to Optimize Attention Accelerator Design
Nandeeka Nayak, Xinrui Wu, Toluwanimi O. Odemuyiwa +3
Attention for transformers is a critical workload that has recently received significant "attention" as a target for custom acceleration. Yet, while prior work succeeds in reducing…
Characterizing the Accuracy -- Efficiency Trade-off of Low-rank Decomposition in Language Models
Chakshu Moar, Faraz Tahmasebi, Michael Pellauer +1
Recent large language models (LLMs) employ billions of parameters to enable broad problem-solving capabilities. Such language models also tend to be memory-bound because of the dom…
TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators
Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare +3
Over the past few years, the explosion in sparse tensor algebra workloads has led to a corresponding rise in domain-specific accelerators to service them. Due to the irregularity p…
CELLO: Co-designing Schedule and Hybrid Implicit/Explicit Buffer for Complex Tensor Reuse
Raveesh Garg, Michael Pellauer, Sivasankaran Rajamanickam +1
Tensor algebra accelerators have been gaining popularity for running high-performance computing (HPC) workloads. Identifying optimal schedules for individual tensor operations and…
Flexagon: A Multi-Dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing
Francisco Muñoz-Martínez, Raveesh Garg, José L. Abellán +3
Sparsity is a growing trend in modern DNN models. Existing Sparse-Sparse Matrix Multiplication (SpMSpM) accelerators are tailored to a particular SpMSpM dataflow (i.e., Inner Produ…
A Formalism of DNN Accelerator Flexibility
Sheng-Chun Kao, Hyoukjun Kwon, Michael Pellauer +2
The high efficiency of domain-specific hardware accelerators for machine learning (ML) has come from specialization, with the trade-off of less configurability/ flexibility. There…
DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators
Sheng-Chun Kao, Michael Pellauer, Angshuman Parashar +1
The design of DNN accelerators includes two key parts: HW resource configuration and mapping strategy. Intensive research has been conducted to optimize each of them independently.…
Enabling Flexibility for Sparse Tensor Acceleration via Heterogeneity
Eric Qin, Raveesh Garg, Abhimanyu Bambhaniya +5
Recently, numerous sparse hardware accelerators for Deep Neural Networks (DNNs), Graph Neural Networks (GNNs), and scientific computing applications have been proposed. A common ch…
Self-Adaptive Reconfigurable Arrays (SARA): Using ML to Assist Scaling GEMM Acceleration
Ananda Samajdar, Michael Pellauer, Tushar Krishna
With increasing diversity in Deep Neural Network(DNN) models in terms of layer shapes and sizes, the research community has been investigating flexible/reconfigurable accelerator s…
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach Using MAESTRO
Hyoukjun Kwon, Prasanth Chatarasi, Michael Pellauer +3
The data partitioning and scheduling strategies used by DNN accelerators to leverage reuse and perform staging are known as dataflow, and they directly impact the performance and e…
UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition
Kartik Hegde, Jiyong Yu, Rohit Agrawal +3
Convolutional Neural Networks (CNNs) have begun to permeate all corners of electronic society (from voice recognition to scene generation) due to their high accuracy and machine ef…
Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler Mappings
Yatin A. Manerkar, Caroline Trippel, Daniel Lustig +2
The C and C++ high-level languages provide programmers with atomic operations for writing high-performance concurrent code. At the assembly language level, C and C++ atomics get ma…
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig +2
Memory consistency models (MCMs) which govern inter-module interactions in a shared memory system, are a significant, yet often under-appreciated, aspect of system design. MCMs are…