3 citations · 4 across the 3 of their papers we have counts for
3 papers
cs.AR2018
Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost
Donghyuk Lee, Yoongu Kim, Vivek Seshadri +3
This paper summarizes the idea of Tiered-Latency DRAM (TL-DRAM), which was published in HPCA 2013, and examines the work's significance and future potential. The capacity and cost-…
cs.AR2018★ 3 cited
Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism
Yoongu Kim, Vivek Seshadri, Donghyuk Lee +2
This paper summarizes the idea of Subarray-Level Parallelism (SALP) in DRAM, which was published in ISCA 2012, and examines the work's significance and future potential. Modern DRA…
cs.AR2016★ 1 cited
Tiered-Latency DRAM (TL-DRAM)
Donghyuk Lee, Yoongu Kim, Vivek Seshadri +3
This paper summarizes the idea of Tiered-Latency DRAM, which was published in HPCA 2013. The key goal of TL-DRAM is to provide low DRAM latency at low cost, a critical problem in m…