2 papers
cs.CL2022
An Executable Formal Model of the VHDL in Isabelle/HOL
Wilayat Khan, Zhe Hou, David Sanan +3
In the hardware design process, hardware components are usually described in a hardware description language. Most of the hardware description languages, such as Verilog and VHDL,…
cs.CL2018
Towards Robust Neural Machine Translation
Yong Cheng, Zhaopeng Tu, Fandong Meng +2
Small perturbations in the input can severely distort intermediate representations and thus impact translation quality of neural machine translation (NMT) models. In this paper, we…