most citedeBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex

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cs.AR2019

Clock Tree Generation by Abutment in Synchoros VLSI Design

Dimitrios Stathis, Panagiotis Chaourani, Syed M. A. H. Jafri +1

Synchoros VLSI design style has been proposed as an alternative to standard cell-based design. Standard cells are replaced by synchoros, large grain, VLSI design objects called SiL…

cs.AR2019★ 4 cited

Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators

Syed M. A. H. Jafri, Hasan Hassan, Ahmed Hemani +1

To employ a Convolutional Neural Network (CNN) in an energy-constrained embedded system, it is critical for the CNN implementation to be highly energy efficient. Many recent studie…