14 citations · 23 across the 4 of their papers we have counts for
4 papers
VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs
Geonhwa Jeong, Sana Damani, Abhimanyu Rajeshkumar Bambhaniya +5
Deep Learning (DL) acceleration support in CPUs has recently gained a lot of traction, with several companies (Arm, Intel, IBM) announcing products with specialized matrix engines…
RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU
Geonhwa Jeong, Eric Qin, Ananda Samajdar +4
As AI-based applications become pervasive, CPU vendors are starting to incorporate matrix engines within the datapath to boost efficiency. Systolic arrays have been the premier arc…
SparseTrain:Leveraging Dynamic Sparsity in Training DNNs on General-Purpose SIMD Processors
Zhangxiaowen Gong, Houxiang Ji, Christopher Fletcher +2
Our community has greatly improved the efficiency of deep learning applications, including by exploiting sparsity in inputs. Most of that work, though, is for inference, where weig…
Banshee: Bandwidth-Efficient DRAM Caching Via Software/Hardware Cooperation
Xiangyao Yu, Christopher J. Hughes, Nadathur Satish +2
Putting the DRAM on the same package with a processor enables several times higher memory bandwidth than conventional off-package DRAM. Yet, the latency of in-package DRAM is not a…