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cs.AR2020★ 1 cited
Analytical Modeling the Multi-Core Shared Cache Behavior with Considerations of Data-Sharing and Coherence
Ming Ling, Xiaoqian Lu, Guangmin Wang +1
To mitigate the ever worsening "Power wall" and "Memory wall" problems, multi-core architectures with multilevel cache hierarchies have been widely accepted in modern processors. H…
cs.AR2019
Fast Modeling L2 Cache Reuse Distance Histograms Using Combined Locality Information from Software Traces
Ming Ling, Jiancong Ge, Guangmin Wang
To mitigate the performance gap between CPU and the main memory, multi-level cache architectures are widely used in modern processors. Therefore, modeling the behaviors of the down…