19 citations · 20 across the 4 of their papers we have counts for
4 papers
A Timing Yield Model for SRAM Cells in Sub/Near-threshold Voltages Based on A Compact Drain Current Model
Shan Shen, Peng Cao, Ming Ling +1
Sub/Near-threshold static random-access memory (SRAM) design is crucial for addressing the memory bottleneck in energy-constrained applications. However, the high integration densi…
Analytical Modeling the Multi-Core Shared Cache Behavior with Considerations of Data-Sharing and Coherence
Ming Ling, Xiaoqian Lu, Guangmin Wang +1
To mitigate the ever worsening "Power wall" and "Memory wall" problems, multi-core architectures with multilevel cache hierarchies have been widely accepted in modern processors. H…
Fast Modeling L2 Cache Reuse Distance Histograms Using Combined Locality Information from Software Traces
Ming Ling, Jiancong Ge, Guangmin Wang
To mitigate the performance gap between CPU and the main memory, multi-level cache architectures are widely used in modern processors. Therefore, modeling the behaviors of the down…
TS Cache: A Fast Cache with Timing-speculation Mechanism Under Low Supply Voltages
Shan Shen, Tianxiang Shao, Xiaojing Shang +4
To mitigate the ever-worsening Power Wall problem, more and more applications need to expand their power supply to the wide-voltage range including the near-threshold region. Howev…