4 citations · 7 across the 4 of their papers we have counts for
8 papers
Hardware-accelerated graph neural networks: an alternative approach for neuromorphic event-based audio classification and keyword spotting on SoC FPGA
Kamil Jeziorek, Piotr Wzorek, Krzysztof Blachut +6
As the volume of data recorded by embedded edge sensors increases, particularly from neuromorphic devices producing discrete event streams, there is a growing need for hardware-awa…
Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA
Hiroshi Nakano, Krzysztof Blachut, Kamil Jeziorek +6
As the quantities of data recorded by embedded edge sensors grow, so too does the need for intelligent local processing. Such data often comes in the form of time-series signals, b…
Utilisation of Vision Systems and Digital Twin for Maintaining Cleanliness in Public Spaces
Mateusz Wasala, Krzysztof Blachut, Hubert Szolc +3
Nowadays, the increasing demand for maintaining high cleanliness standards in public spaces results in the search for innovative solutions. The deployment of CCTV systems equipped…
Embedded Graph Convolutional Networks for Real-Time Event Data Processing on SoC FPGAs
Kamil Jeziorek, Piotr Wzorek, Krzysztof Blachut +2
The utilisation of event cameras represents an important and swiftly evolving trend aimed at addressing the constraints of traditional video systems. Particularly within the automo…
Optimising Graph Representation for Hardware Implementation of Graph Convolutional Networks for Event-based Vision
Kamil Jeziorek, Piotr Wzorek, Krzysztof Blachut +2
Event-based vision is an emerging research field involving processing data generated by Dynamic Vision Sensors (neuromorphic cameras). One of the latest proposals in this area are…
High-definition event frame generation using SoC FPGA devices
Krzysztof Blachut, Tomasz Kryjak
In this paper we have addressed the implementation of the accumulation and projection of high-resolution event data stream (HD -1280 x 720 pixels) onto the image plane in FPGA devi…