activity
20162026
most citedEnabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism

5 citations · 6 across the 9 of their papers we have counts for

collaborators

10 papers

cs.NI2026

Throughput-Optimized Networks at Scale

Conor Green, Conor James Green, Mithuna Thottethodi +1

Data center network design plays a critical role in AI training by supporting scaling to thousands of accelerators. An open problem, designing a near-optimal throughput-oriented ne…

cs.AR2024

Efficient Sparse Processing-in-Memory Architecture (ESPIM) for Machine Learning Inference

Mingxuan He, Mithuna Thottethodi, T. N. Vijaykumar

Emerging machine learning (ML) models (e.g., transformers) involve memory pin bandwidth-bound matrix-vector (MV) computation in inference. By avoiding pin crossings, processing in…

cs.AR2024

QED: Scalable Verification of Hardware Memory Consistency

Gokulan Ravi, Xiaokang Qiu, Mithuna Thottethodi +1

Memory consistency model (MCM) issues in out-of-order-issue microprocessor-based shared-memory systems are notoriously non-intuitive and a source of hardware design bugs. Prior har…

cs.AR2024

NetSmith: An Optimization Framework for Machine-Discovered Network Topologies

Conor Green, Mithuna Thottethodi

Over the past few decades, network topology design for general purpose, shared memory multicores has been primarily driven by human experts who use their insights to arrive at netw…

cs.AR2023★ 1 cited

SafeBet: Secure, Simple, and Fast Speculative Execution

Conor Green, Cole Nelson, Mithuna Thottethodi +1

Spectre attacks exploit microprocessor speculative execution to read and transmit forbidden data outside the attacker's trust domain and sandbox. Recent hardware schemes allow pote…

cs.AR2021

OCCAM: Optimal Data Reuse for Convolutional Neural Networks

Ashish Gondimalla, Jianqiao Liu, T. N. Vijaykumar +1

Convolutional neural networks (CNNs) are emerging as powerful tools for image processing in important commercial applications. We focus on the important problem of improving the la…

cs.AR2021

Barrier-Free Large-Scale Sparse Tensor Accelerator (BARISTA) For Convolutional Neural Networks

Ashish Gondimalla, Sree Charan Gundabolu, T. N. Vijaykumar +1

Convolutional neural networks (CNNs) are emerging as powerful tools for visual recognition. Recent architecture proposals for sparse CNNs exploit zeros in the feature maps and filt…

cs.AR2020

Booster: An Accelerator for Gradient Boosting Decision Trees

Mingxuan He, T. N. Vijaykumar, Mithuna Thottethodi

We propose Booster, a novel accelerator for gradient boosting trees based on the unique characteristics of gradient boosting models. We observe that the dominant steps of gradient…

cs.NI2018

Dart: Divide and Specialize for Fast Response to Congestion in RDMA-based Datacenter Networks

Jiachen Xue, Muhammad Usama Chaudhry, Balajee Vamanan +2

Though Remote Direct Memory Access (RDMA) promises to reduce datacenter network latencies significantly compared to TCP (e.g., 10x), end-to-end congestion control in the presence o…

cs.AR2016★ 5 cited

Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism

Kevin K. Chang, Gabriel H. Loh, Mithuna Thottethodi +6

Die-stacked DRAM has been proposed for use as a large, high-bandwidth, last-level cache with hundreds or thousands of megabytes of capacity. Not all workloads (or phases) can produ…