36 citations · 78 across the 9 of their papers we have counts for
7 papers · 1 filter
Machine Learning for Microprocessor Performance Bug Localization
Erick Carvajal Barboza, Mahesh Ketkar, Michael Kishinevsky +2
The validation process for microprocessors is a very complex task that consumes substantial engineering time during the design process. Bugs that degrade overall system performance…
The Championship Simulator: Architectural Simulation for Education and Competition
Nathan Gober, Gino Chacon, Lei Wang +5
Recent years have seen a dramatic increase in the microarchitectural complexity of processors. This increase in complexity presents a twofold challenge for the field of computer ar…
Reducing Minor Page Fault Overheads through Enhanced Page Walker
Chandrahas Tirumalasetty, Chih Chieh Chou, Narasimha Reddy +2
Application virtual memory footprints are growing rapidly in all systems from servers down to smartphones. To address this growing demand, system integrators are incorporating ever…
Coherence Attacks and Countermeasures in Interposer-Based Systems
Gino Chacon, Tapojyoti Mandal, Johann Knechtel +3
Industry is moving towards large-scale systems where processor cores, memories, accelerators, etc.\ are bundled via 2.5D integration. These various components are fabricated separa…
Automatic Microprocessor Performance Bug Detection
Erick Carvajal Barboza, Sara Jacob, Mahesh Ketkar +3
Processor design validation and debug is a difficult and complex task, which consumes the lion's share of the design process. Design bugs that affect processor performance rather t…
FPGA-based Hyrbid Memory Emulation System
Fei Wen, Mian Qin, Paul V. Gratz +1
Hybrid memory systems, comprised of emerging non-volatile memory (NVM) and DRAM, have been proposed to address the growing memory demand of applications. Emerging NVM technologies,…
Hardware Memory Management for Future Mobile Hybrid Memory Systems
Fei Wen, Mian Qin, Paul Gratz +1
The current mobile applications have rapidly growing memory footprints, posing a great challenge for memory system design. Insufficient DRAM main memory will incur frequent data sw…