most citedRVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions

1 citations · 1 across the 1 of their papers we have counts for

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2 papers

cs.AR2020★ 1 cited

RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions

Takuto Kanamori, Hiromu Miyazaki, Kenji Kise

In this paper, we propose a high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions targeting on FPGA. The compressed instruction…

cs.AR2020

RVCoreP : An optimized RISC-V soft processor of five-stage pipelining

Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam +1

RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basi…