91 citations · 183 across the 12 of their papers we have counts for
13 papers
PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
Qijun Zhang, Shiyu Li, Guanglei Zhou +4
Power efficiency is a critical design objective in modern microprocessor design. To evaluate the impact of architectural-level design decisions, an accurate yet efficient architect…
EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research
Jingyu Pan, Chen-Chia Chang, Zhiyao Xie +2
The application of Machine Learning (ML) in Electronic Design Automation (EDA) for Very Large-Scale Integration (VLSI) design has garnered significant research attention. Despite t…
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
Wenji Fang, Yao Lu, Shang Liu +5
In modern VLSI design flow, the register-transfer level (RTL) stage is a critical point, where designers define precise design behavior with hardware description languages (HDLs) l…
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
Yao Lu, Shang Liu, Qijun Zhang +1
Inspired by the recent success of large language models (LLMs) like ChatGPT, researchers start to explore the adoption of LLMs for agile hardware design, such as generating design…
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs
Linfeng Du, Tingyuan Liang, Sharad Sinha +2
Multi-die FPGAs are widely adopted to deploy large hardware accelerators. Two factors impede the performance optimization of HLS designs implemented on multi-die FPGAs. On the one…
Intelligent Circuit Design and Implementation with Machine Learning
Zhiyao Xie
The stagnation of EDA technologies roots from insufficient knowledge reuse. In practice, very similar simulation or optimization results may need to be repeatedly constructed from…