91 citations · 183 across the 13 of their papers we have counts for
13 papers
PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
Qijun Zhang, Shiyu Li, Guanglei Zhou +4
Power efficiency is a critical design objective in modern microprocessor design. To evaluate the impact of architectural-level design decisions, an accurate yet efficient architect…
EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research
Jingyu Pan, Chen-Chia Chang, Zhiyao Xie +2
The application of Machine Learning (ML) in Electronic Design Automation (EDA) for Very Large-Scale Integration (VLSI) design has garnered significant research attention. Despite t…
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
Wenji Fang, Yao Lu, Shang Liu +5
In modern VLSI design flow, the register-transfer level (RTL) stage is a critical point, where designers define precise design behavior with hardware description languages (HDLs) l…
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
Yao Lu, Shang Liu, Qijun Zhang +1
Inspired by the recent success of large language models (LLMs) like ChatGPT, researchers start to explore the adoption of LLMs for agile hardware design, such as generating design…
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs
Linfeng Du, Tingyuan Liang, Sharad Sinha +2
Multi-die FPGAs are widely adopted to deploy large hardware accelerators. Two factors impede the performance optimization of HLS designs implemented on multi-die FPGAs. On the one…
Intelligent Circuit Design and Implementation with Machine Learning
Zhiyao Xie
The stagnation of EDA technologies roots from insufficient knowledge reuse. In practice, very similar simulation or optimization results may need to be repeatedly constructed from…
The Dark Side: Security Concerns in Machine Learning for EDA
Zhiyao Xie, Jingyu Pan, Chen-Chia Chang +1
The growing IC complexity has led to a compelling need for design efficiency improvement through new electronic design automation (EDA) methodologies. In recent years, many unprece…
Towards Collaborative Intelligence: Routability Estimation based on Decentralized Private Data
Jingyu Pan, Chen-Chia Chang, Zhiyao Xie +5
Applying machine learning (ML) in design flow is a popular trend in EDA with various applications from design quality predictions to optimizations. Despite its promise, which has b…
Automatic Routability Predictor Development Using Neural Architecture Search
Chen-Chia Chang, Jingyu Pan, Tunhou Zhang +8
The rise of machine learning technology inspires a boom of its applications in electronic design automation (EDA) and helps improve the degree of automation in chip designs. Howeve…
Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation
Zhiyao Xie, Rongjian Liang, Xiaoqing Xu +3
Net length is a key proxy metric for optimizing timing and power across various stages of a standard digital design flow. However, the bulk of net length information is not availab…
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network
Zhiyao Xie, Haoxing Ren, Brucek Khailany +4
IR drop is a fundamental constraint required by almost all chip designs. However, its evaluation usually takes a long time that hinders mitigation techniques for fixing its violati…
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning
Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang +7
Design flow parameters are of utmost importance to chip design quality and require a painfully long time to evaluate their effects. In reality, flow parameter tuning is usually per…
Fast IR Drop Estimation with Machine Learning
Zhiyao Xie, Hai Li, Xiaoqing Xu +2
IR drop constraint is a fundamental requirement enforced in almost all chip designs. However, its evaluation takes a long time, and mitigation techniques for fixing violations may…