71 citations · 78 across the 6 of their papers we have counts for
7 papers
NDS: Programmer-Free Offload of High-Performance Near Data Strands
Shreyas Singh, Pratyush Nandi, Lin Jia +2
Near Data Processing (NDP) has the potential to significantly improve system performance and energy by alleviating data movement bottlenecks. However, most NDP proposals pose heavy…
Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction
Rahul Bera, Konstantinos Kanellopoulos, Shankar Balachandran +4
Long-latency load requests continue to limit the performance of high-performance processors. To increase the latency tolerance of a processor, architects have primarily relied on t…
Proximu$: Efficiently Scaling DNN Inference in Multi-core CPUs through Near-Cache Compute
Anant V. Nori, Rahul Bera, Shankar Balachandran +5
Deep Neural Network (DNN) inference is emerging as the fundamental bedrock for a multitude of utilities and services. CPUs continue to scale up their raw compute capabilities for D…
Compiler Enhanced Scheduling for OpenMP for Heterogeneous Multiprocessors
Jyothi Krishna V S, Shankar Balachandran
Scheduling in Asymmetric Multicore Processors (AMP), a special case of Heterogeneous Multiprocessors, is a widely studied topic. The scheduling techniques which are mostly runtime…
Fast-SL: An efficient algorithm to identify synthetic lethal reaction sets in metabolic networks
Aditya Pratapa, Shankar Balachandran, Karthik Raman
Synthetic lethal reaction/gene-sets are sets of reactions/genes where only the simultaneous removal of all reactions/genes in the set abolishes growth of an organism. In silico, sy…
A Study on Hierarchical Floorplans of Order k
Shankar Balachandran, Sajin Koroth
A floorplan is a rectangular dissection which describes the relative placement of electronic modules on the chip. It is called a mosaic floorplan if there are no empty rooms or cro…
Sub-families of Baxter Permutations Based on Pattern Avoidance
Shankar Balachandran, Sajin Koroth
Baxter permutations are a class of permutations which are in bijection with a class of floorplans that arise in chip design called mosaic floorplans. We study a subclass of mosaic…