10 citations · 13 across the 4 of their papers we have counts for
6 papers
SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures
Cristian Tirelli, Lorenzo Ferretti, Laura Pozzi
Coarse-Grain Reconfigurable Arrays (CGRAs) are emerging low-power architectures aimed at accelerating compute-intensive application loops. The acceleration that a CGRA can ultimate…
SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs
Cristian Tirelli, Juan Sapriza, Rubén Rodríguez Álvarez +6
Coarse-Grain Reconfigurable Arrays (CGRAs) represent emerging low-power architectures designed to accelerate Compute-Intensive Loops (CILs). The effectiveness of CGRAs in providing…
HyperPUT: Generating Synthetic Faulty Programs to Challenge Bug-Finding Tools
Riccardo Felici, Laura Pozzi, Carlo A. Furia
As research in automatically detecting bugs grows and produces new techniques, having suitable collections of programs with known bugs becomes crucial to reliably and meaningfully…
A Graph Deep Learning Framework for High-Level Synthesis Design Space Exploration
Lorenzo Ferretti, Andrea Cini, Georgios Zacharopoulos +2
The design of efficient hardware accelerators for high-throughput data-processing applications, e.g., deep neural networks, is a challenging task in computer architecture design. I…
DB4HLS: A Database of High-Level Synthesis Design Space Explorations
Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni +3
High-Level Synthesis (HLS) frameworks allow to easily specify a large number of variants of the same hardware design by only acting on optimization directives. Nonetheless, the har…
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Partha Biswas, Sudarshan Banerjee, Nikil Dutt +2
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qual…