55 citations · 65 across the 8 of their papers we have counts for
8 papers
QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL
Lennart M. Reimann, Anshul Prashar, Chiara Ghinami +4
In contemporary Electronic Design Automation (EDA) tools, security often takes a backseat to the primary goals of power, performance, and area optimization. Commonly, the security…
Quantitative Information Flow for Hardware: Advancing the Attack Landscape
Lennart M. Reimann, Sarp Erdönmez, Dominik Sisejkovic +1
Security still remains an afterthought in modern Electronic Design Automation (EDA) tools, which solely focus on enhancing performance and reducing the chip size. Typically, the se…
Designing ML-Resilient Locking at Register-Transfer Level
Dominik Sisejkovic, Luca Collini, Benjamin Tan +3
Various logic-locking schemes have been proposed to protect hardware from intellectual property piracy and malicious design modifications. Since traditional locking techniques are…
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation
Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel +5
Memristor-based crossbar arrays represent a promising emerging memory technology to replace conventional memories by offering a high density and enabling computing-in-memory (CIM)…
pHGen: A pH-Based Key Generation Mechanism Using ISFETs
Elmira Moussavi, Dominik Sisejkovic, Fabian Brings +7
Digital keys are a fundamental component of many hardware- and software-based security mechanisms. However, digital keys are limited to binary values and easily exploitable when st…
Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks
Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann +1
Logic locking has emerged as a prominent key-driven technique to protect the integrity of integrated circuits. However, novel machine-learning-based attacks have recently been intr…