85 citations · 287 across the 21 of their papers we have counts for
26 papers
SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors
Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic +2
Despite its ever-increasing impact, security is not considered as a design objective in commercial electronic design automation (EDA) tools. This results in vulnerabilities being o…
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style
Simranjeet Singh, Chandan Kumar Jha, Ankit Bende +5
Memristor-based logic-in-memory (LiM) has become popular as a means to overcome the von Neumann bottleneck in traditional data-intensive computing. Recently, the memristor-aided lo…
IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines
Omar Ghazal, Simranjeet Singh, Tousif Rahman +8
In-memory computing for Machine Learning (ML) applications remedies the von Neumann bottlenecks by organizing computation to exploit parallelism and locality. Non-volatile memory d…
Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar
Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran +4
This paper proposes an architecture that integrates neural networks (NNs) and hardware security modules using a single resistive random access memory (RRAM) crossbar. The proposed…
Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic
Elmira Moussavi, Animesh Singh, Dominik Sisejkovic +6
Most chip designers outsource the manufacturing of their integrated circuits (ICs) to external foundries due to the exorbitant cost and complexity of the process. This involvement…
Finite State Automata Design using 1T1R ReRAM Crossbar
Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha +6
Data movement costs constitute a significant bottleneck in modern machine learning (ML) systems. When combined with the computational complexity of algorithms, such as neural netwo…
Hardware Security Primitives using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs
Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran +3
With rapid advancements in electronic gadgets, the security and privacy aspects of these devices are significant. For the design of secure systems, physical unclonable function (PU…
A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications
Elmira Moussavi, Dominik Sisejkovic, Animesh Singh +5
The ion-sensitive field-effect transistor (ISFET) is an emerging technology that has received much attention in numerous research areas, including biochemistry, medicine, and secur…
PA-PUF: A Novel Priority Arbiter PUF
Simranjeet Singh, Srinivasu Bodapati, Sachin Patkar +3
This paper proposes a 3-input arbiter-based novel physically unclonable function (PUF) design. Firstly, a 3-input priority arbiter is designed using a simple arbiter, two multiplex…
pHGen: A pH-Based Key Generation Mechanism Using ISFETs
Elmira Moussavi, Dominik Sisejkovic, Fabian Brings +7
Digital keys are a fundamental component of many hardware- and software-based security mechanisms. However, digital keys are limited to binary values and easily exploitable when st…
A Parallel SystemC Virtual Platform for Neuromorphic Architectures
Melvin Galicia, Farhad Merchant, Rainer Leupers
With the increasing interest in neuromorphic computing, designers of embedded systems face the challenge of efficiently simulating such platforms to enable architecture design expl…
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories
Felix Staudigl, Hazem Al Indari, Daniel Schön +6
Emerging non-volatile memory (NVM) technologies offer unique advantages in energy efficiency, latency, and features such as computing-in-memory. Consequently, emerging NVM technolo…
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog
Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic +2
The enormous amount of code required to design modern hardware implementations often leads to critical vulnerabilities being overlooked. Especially vulnerabilities that compromise…
Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks
Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann +1
Logic locking has emerged as a prominent key-driven technique to protect the integrity of integrated circuits. However, novel machine-learning-based attacks have recently been intr…
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities
Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi +2
In the past decade, a lot of progress has been made in the design and evaluation of logic locking; a premier technique to safeguard the integrity of integrated circuits throughout…
Brightening the Optical Flow through Posit Arithmetic
Vinay Saxena, Ankitha Reddy, Jonathan Neudorfer +4
As new technologies are invented, their commercial viability needs to be carefully examined along with their technical merits and demerits. The posit data format, proposed as a dro…
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework
Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann +3
With the growing demands of consumer electronic products, the computational requirements are increasing exponentially. Due to the applications' computational needs, the computer ar…
An Investigation on Inherent Robustness of Posit Data Representation
Ihsen Alouani, Anouar Ben Khalifa, Farhad Merchant +1
As the dimensions and operating voltages of computer electronics shrink to cope with consumers' demand for higher performance and lower power consumption, circuit sensitivity to so…
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach
Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann +3
Logic locking is a prominent technique to protect the integrity of hardware designs throughout the integrated circuit design and fabrication flow. However, in recent years, the sec…
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems
Suresh Nambi, Salim Ullah, Aditya Lohana +3
The recent advances in machine learning, in general, and Artificial Neural Networks (ANN), in particular, has made smart embedded systems an attractive option for a larger number o…
CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism
Niraj Sharma, Riya Jain, Madhumita Mohan +4
Many engineering and scientific applications require high precision arithmetic. IEEE~754-2008 compliant (floating-point) arithmetic is the de facto standard for performing these co…
Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay +4
We present efficient realization of Generalized Givens Rotation (GGR) based QR factorization that achieves 3-100x better performance in terms of Gflops/watt over state-of-the-art r…
Achieving Efficient Realization of Kalman Filter on CGRA through Algorithm-Architecture Co-design
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay +3
In this paper, we present efficient realization of Kalman Filter (KF) that can achieve up to 65% of the theoretical peak performance of underlying architecture platform. KF is real…
Efficient Realization of Householder Transform through Algorithm-Architecture Co-design for Acceleration of QR Factorization
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay +3
We present efficient realization of Householder Transform (HT) based QR factorization through algorithm-architecture co-design where we achieve performance improvement of 3-90x in-…