17 citations · 19 across the 2 of their papers we have counts for
2 papers
cs.LG2023★ 17 cited
VerilogEval: Evaluating Large Language Models for Verilog Code Generation
Mingjie Liu, Nathaniel Pinckney, Brucek Khailany +1
The increasing popularity of large language models (LLMs) has paved the way for their application in diverse domains. This paper proposes a benchmarking framework tailored specific…
cs.LO2021★ 2 cited
Verifying High-Level Latency-Insensitive Designs with Formal Model Checking
Steve Dai, Alicia Klinefelter, Haoxing Ren +4
Latency-insensitive design mitigates increasing interconnect delay and enables productive component reuse in complex digital systems. This design style has been adopted in high-lev…