2 citations · 2 across the 1 of their papers we have counts for
2 papers
cs.LO2021★ 2 cited
Verifying High-Level Latency-Insensitive Designs with Formal Model Checking
Steve Dai, Alicia Klinefelter, Haoxing Ren +4
Latency-insensitive design mitigates increasing interconnect delay and enables productive component reuse in complex digital systems. This design style has been adopted in high-lev…
cs.AR2020
MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification
Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren +3
Vectored IR drop analysis is a critical step in chip signoff that checks the power integrity of an on-chip power delivery network. Due to the prohibitive runtimes of dynamic IR dro…